1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods of forming semiconductor devices using a novel process flow that involves a reduced number of spacers.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout. Metal oxide field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. A FET (whether an NFET or a PFET) is a device that typically includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region. A gate insulation layer is positioned between the gate electrode and the channel region that will be formed in the substrate. Electrical contacts are made to the source and drain regions, and current flow through the FET is controlled by controlling the voltage applied to the gate electrode. If there is no voltage applied to the gate electrode, then there is no current flow through the device (ignoring undesirable leakage currents, which are relatively small). However, when an appropriate voltage is applied to the gate electrode, the channel region becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region. Traditionally, FETs have been substantially planar devices, but similar principles of operation apply to more three-dimensional FET structures, devices that are typically referred to as FinFETs.
The formation of transistors typically involves performing one or more ion implantation processes to form various doped regions in the substrate, such as halo implant regions, extension implant regions and deep source/drain implant regions. In many of the cases, one or more spacers are formed adjacent a gate electrode structure so as to control the location of the various implant regions. Typically, these spacers are made of silicon nitride to facilitate processing. More specifically, silicon nitride is often selected because it can be readily etched, and thus removed, relative to a silicon substrate and an underlying silicon dioxide liner layer which is frequently present to act as an etch stop layer when the silicon nitride spacer is removed.
FIGS. 1A-1G depict one illustrative prior art process flow for forming a semiconductor device 100 that includes an illustrative PFET transistor 100P and an illustrative NFET transistor 100N using an illustrative combination of silicon nitride spacers. As shown in FIG. 1A, the process begins with the formation of illustrative gate structures 14 for the PFET transistor 100P and the NFET transistor 100N in and above regions of the substrate 10 that are separated by an illustrative shallow trench isolation structure 12. The gate structures 14 generally include a gate insulation layer 14A and one or more conductive gate electrode layers 14B. A gate cap layer 16, made of a material such as silicon nitride, is formed above the gate structures 14. Also depicted in FIG. 1A is an illustrative liner layer 18, made of a material such as silicon dioxide having a thickness of approximately 3-5 nm, that is conformally deposited on the device 100. The gate structures 14 depicted herein are intended to be schematic and representative in nature, as the materials of construction used in the gate structures 14 may be different for the PFET transistor 100P as compared to the NFET transistor 100N, e.g., the PFET transistor 100P may have multiple layers of conductive metal, etc. The gate insulation layer 14A may be comprised of a variety of materials, such as silicon dioxide, silicon oxynitride, a high-k (k value greater than 10) insulating material. The gate electrode layer 14B may be comprised of one or more layers of conductive materials, such as polysilicon, a metal, etc. The structure depicted in FIG. 1A may be formed by performing a variety of known techniques. For example, the layers of material that make up the gate insulation layer 14A, the gate electrode layer 14B and the gate cap layer 16 may be blanket-deposited above the substrate 10 and, thereafter, one or more etching process are performed through a patterned mask layer (not shown) to define the basic structures depicted in FIG. 1A. Thereafter, a conformal deposition process is performed to form the liner layer 18.
FIG. 1B depicts the device 100 after several process operations have been performed. More specifically, illustrative first sidewall spacers 20 (e.g., silicon nitride) with an illustrative base width of about 5-10 nm are formed adjacent the liner layer 18 for both the PFET transistor 100P and the NFET transistor 100N. The first spacers 20 may be formed by depositing a layer of spacer material and thereafter performing an anisotropic etching process. Exposed horizontal portions of the oxide liner layer 18 are removed after the spacers 20 are formed. Next, a masking layer (not shown), such as a photoresist mask, is formed so as to cover the NFET transistor 100N and expose the PFET transistor 100P for further processing. Then, one or more ion implantation processes are performed on the exposed PFET transistor 100P to form various doped regions in the substrate 10. More specifically, at the point depicted in FIG. 1B, an angled ion implant process may be performed using an N-type dopant material to form so-called halo implant regions 21P in the substrate 10 for the PFET transistor 100P, and another vertical ion implantation process may be performed using a P-type dopant material to form extension implant regions 23P for the PFET transistor 100P. Thereafter, a very quick anneal process, such as a laser anneal process, may be performed at a temperature of about 1250° C. for about 10 milliseconds or so to repair the damaged lattice structure of the substrate 10 in the areas that were subjected to the ion implantation processes discussed above. The implant regions 21P, 23P are depicted schematically and they are located in a position where they will be after the anneal process has been performed, where some migration of the implanted dopant material may have occurred.
FIG. 1C also depicts the device 100 after several process operations have been performed on the device 100. More specifically, a hard mask layer 17, made of a material such as silicon nitride, is formed above the NFET transistor 100N and the PFET transistor 100P. The hard mask layer 17 may be formed by blanket-depositing the hard mask layer 17 across the device 100 and, thereafter, forming a masking layer (not shown), such as a photo-resist mask, so as to cover the NFET transistor 100N and expose the PFET transistor 100P for further processing. Then, an anisotropic etching process is performed to remove the hard mask layer 17 from above the PFET transistor 100P. This process results in the formation of a second sidewall spacer 22 adjacent the first sidewall spacer 20 on the PFET transistor 100P. In some embodiments, the second spacer 22 may have a base width of about 4-8 nm. Next, one or more etching processes are performed to define cavities 24 in areas of the substrate 10 where source/drain regions for the PFET transistor 100P will ultimately be formed. The depth and shape of the cavities 24 may vary depending upon the particular application. In one example, where the cavities 24 have an overall depth 25 of about 70 nm, the cavities 24 may be formed by performing an initial dry anisotropic etching process to a depth of about 40-50 nm and, thereafter, performing a wet etching process using, for example TMAH, which has an etch rate that varies based upon the crystalline structure of the substrate 10, e.g., the etching process using TMAH exhibits a higher etch rate in the 110 direction than it does in the 100 direction.
FIG. 1D depicts the device 100 after an epitaxial deposition process is performed to form epitaxial silicon/germanium regions 26 in the cavities 24 (FIG. 1C). In the depicted example, the regions 26 have an overfill portion that extends above the surface 10S of the substrate 10. In the depicted example, the uppermost surface of the epitaxial silicon/germanium regions 26 extends above the substrate 10 by a distance 27 of about 25 nm. The regions 26 may be formed by performing well-known epitaxial deposition processes. The device 100 in FIG. 1D has also been subjected to an etching process using, for example, hot phosphoric acid, to remove all of the exposed nitride materials, such as the hard mask layer 17, the first spacers 20, the second spacers 22 and the gate cap layers 16.
As shown in FIG. 1E, any remaining portions of the original liner layer 18 may be removed and new liner layer 18A comprised of, for example, 3-5 nm of silicon dioxide, may be formed in its place. Alternatively, the original liner layer 18 may remain in place. Thereafter, illustrative third sidewall spacers 28 (e.g., silicon nitride) with an illustrative base width of about 5-10 nm are formed adjacent the liner layer 18A for both the PFET transistor 100P and the NFET transistor 100N. The third sidewall spacers 28 may be formed by depositing a layer of spacer material and thereafter performing an anisotropic etching process. Next, a masking layer (not shown), such as a photoresist mask, is formed so as to cover the PFET transistor 100P and expose the NFET transistor 100N for further processing. Then, one or more ion implantation processes are performed on the exposed NFET transistor 100N to form various doped regions in the substrate 10. More specifically, at the point depicted in FIG. 1E, an angled ion implantation process may be performed using a P-type dopant material to form so-called halo implant regions 21N in the substrate 10 for the NFET transistor 100N, and another vertical ion implantation process may be performed using an N-type dopant material to form extension implant regions 23N for the NFET transistor 100N. Thereafter, a very quick anneal process, such as a laser anneal process, may be performed at a temperature of about 1250° C. for about 10 milliseconds or so to repair the damaged lattice structure of the substrate 10 in the areas that were subjected to the ion implantation processes discussed above. The implant regions 21N, 23N are depicted schematically and they are located in a position where they will be after the anneal process has been performed, wherein some migration of the implanted dopant material may have occurred.
Next, as shown in FIG. 1F, a set of fourth sidewall spacers 30 (e.g., silicon nitride) are formed for both the PFET transistor 100P and the NFET transistor 100N. Although not depicted in the drawings, another conformal liner layer of, for example, 3-5 nm of silicon dioxide may be formed so as to cover the third sidewall spacers 28 prior to forming the fourth sidewall spacers 30. Thereafter, deep source/drain ion implantation processes are performed on the PFET transistor 100P and the NFET transistor 100N using appropriate masking layers and appropriate dopant materials, all of which are well known to those skilled in the art, to form P-doped source/drain implant regions 29P on the PFET transistor 100P and N-doped source/drain implant regions 29N on the NFET transistor 100N. One or more anneal processes are then performed to repair lattice damage to the substrate and to activate the implanted dopant material.
FIG. 1G depicts the device 100 after metal silicide regions 32 have been formed on the device 100. More specifically, the metal silicide regions 32 are formed on the gate electrode 14B and on the source/drain regions of the transistors 100P, 100N. So as not to obscure the drawings, the various doped regions described previously are not depicted in FIG. 1G. The metal silicide regions 32 may be made of any metal silicide and they may be formed using traditional silicidation techniques. The metal silicide regions 32 need not be the same metal silicide material on both the PFET transistor 100P and the NFET transistor 100N, although that may be the case. Although not depicted in the drawings, the fabrication of the device 100 would include several additional steps, such as the formation of a plurality of conductive contacts or plugs in a layer of insulating material so as to establish electrical connection with the source/drain regions of the transistors.
The above disclosed technique provides for the formation of four spacers at various points in the process flow. The formation of so many spacers during the above-described process flow provides a mechanism whereby the location of various doped regions may be positioned so as to individually enhance the performance capabilities of the PFET transistor 100P and the NFET transistor 100N. However, the formation of so many spacers does have a downside. More specifically, during the formation of the various spacers, the exposed substrate, i.e., the areas of the substrate where the source/drain regions are to be formed, are also attacked, which leads to undesirable localized recessing of the substrate in those areas. Moreover, the formation of such spacers involves performing multiple process operations for each spacer, i.e., at least the steps that involve the deposition of the spacer material and the subsequent anisotropic etching process that is performed to define each spacer. In some cases, like the one discussed above, the formation of multiple spacers during a particular process flow may also necessitate that an etching process be performed at some point in the process flow to remove one or more of the sidewall spacers. In summary, the process flow described above, wherein four sidewall spacers are formed, involves performing several process operations at great time and expense to the manufacturer, and the performance of so many process steps can lead to additional processing complexity and to damage to other aspects of the transistor device.
The present disclosure is directed to various methods of forming semiconductor devices using a novel process flow that involves a reduced number of spacers that may avoid, or at least reduce, the effects of one or more of the problems identified above.